JFET Biasing

There are two basic types of JFET biasing which are:

1.   Bias Battery
2.   Biasing Circuit

Bias Battery

This method is also called a gate bias. The battery voltage, V_GG ensures that gate source junction remains reverse biased. In this gate bias method there is no gate current therefore there will be no voltage drop across R_G. It is also known as a fixed biasing circuit.

Biasing Circuit

The biasing circuit uses the supply voltage V_DD to provide the necessary bias.
There are two commonly used methods which are:




1.   Self Bias
2.   Potential Divider Bias

Self Bias

In self bias the resistor, R_S is the bias resistor. The d.c. component of drain current flowing through R_S produces the desired bias voltage.
Voltage across R_S, V_S = I_DR_S
Since the gate current is negligibly small, the gate terminal is at d.c. ground is V_G = 0.
V_GS = V_G - V_S
    = 0 - V_S
    = -I_DR_S
Thus bias voltage V_GS keeps gate negative with respect to source.
Midpoint - Bias:  When a signal is applied, the midpoint bias allows a maximum current of drain current swing between I_DSS and 0. It can be proved that when V_GS = V_GS(off)/3.4, midpoint bias conditions are obtained.

Potential Divider Bias

The resistors R₁ and R₂ forms a voltage divider across drain supply, V_DD. The circuit is so designed that I_DR_S is larger than V₂ so that V_GS is negative which provides the correct bias voltage.

V₂ = V_G = V_DD(R_S)/(R₁ + R₂)
V₂ = V_GS + I_DR_S
V_GS = V₂ - I_DR_S

The biasing circuit provides good stability of the operating points.