Negative Clamper

As stated in the previous post,
A clamping circuit is a circuit that places either the positive or negative peak of a signal at a desired d.c. level.

A clamping circuit does not change the peak to peak or root mean square value of a waveform.

The operation of a clamper or clamping circuit is based on the principle that charging time of a capacitor is made very small as compared to its discharging time.

In a practical clamping circuit, the values of C and R_L are chosen that discharging is very large.

Operation of a Negative Clamper:

Negative Clamper

During the positive half cycle of the input signal, the diode is forward biased. Therefore, the diode behaves as a short. The charging time constant (CR_f) is very small where R_f is the forward resistance of the diode.

Therefore, the capacitor will charge to V volts quickly. Since the diode is short there is no output voltage during the positive half cycle of the input signal.

During the negative half cycle of the input signal, the diode is reverse biased and behaves as an open. Since the discharging constant (CR_L) is much greater than the time period of the input signal, the capacitor almost remain fully charged to V volts during the off time of the diode. R_L is the load resistance.

To clarify negative clamping well, I would say that before the charging of the capacitor, the capacitor = 0. After the charging it becomes equal to V volts. During the discharging since its time constant is longer than the time period of the signal it almost remains at V volts. Therefore, the mid - point of the amplitude of the signal is equal to V volts in the negative direction.