Positive Clamper

A clamping circuit is a circuit that places either the positive or negative peak of a signal at a desired d.c. level.

A clamping circuit does not change the peak to peak or root mean square value of a waveform.

The operation of a clamper or clamping circuit is based on the principle that charging time of a capacitor is made very small as compared to its discharging time.

In a practical clamping circuit, the values of C and R_L are chosen that discharging is very large.

Positive Clamper

Operation of a Positive Clamper:

First, the values of C and R_L are selected such that the time constant (CR_L) is very large where R_L is the load resistance.

This means that the voltage across the capacitor will not discharge significantly during the interval the diode is non - conducting.

Second, the time constant is deliberately made much greater than the time period of the incoming signal.

During the positive half cycle of the input signal, the diode is reverse biased and behaves as an open. Since the discharging time constant is much greater than the time period of the input signal, the capacitor remains almost fully charged to V volts during the off time of the diode.

During the negative half cycle of the input signal, the diode is forward biased and behaves as a short. Therefore, current passes through the diode. The charging time constant is CR_f where R_f is the forward resistance of the diode which is also very small so the capacitor charges to V volts quickly.

Therefore, during the positive half cycle of the input signal the output voltage is zero.

In my own understanding, the capacitor = 0 before charging and after charging during discharging it almost remains close to V. Therefore the mid line of the signal at the output should be at V. Therefore, this should explain why the at the output signal the input signal is pushed upwards.